Module zinc_hal_lpc11xx::ioregs

Structs

ADC	10-bit ADC
ADC_cr	Register CR: A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur.
ADC_cr_Get	CR: A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur.
ADC_cr_Update	Updater for CR register.
ADC_dr0	Register DR0: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.
ADC_dr0_Get	DR0: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.
ADC_dr0_Update	Updater for DR0 register.
ADC_dr1	Register DR1: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.
ADC_dr1_Get	DR1: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.
ADC_dr1_Update	Updater for DR1 register.
ADC_dr2	Register DR2: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.
ADC_dr2_Get	DR2: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.
ADC_dr2_Update	Updater for DR2 register.
ADC_dr3	Register DR3: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.
ADC_dr3_Get	DR3: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.
ADC_dr3_Update	Updater for DR3 register.
ADC_dr4	Register DR4: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.
ADC_dr4_Get	DR4: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.
ADC_dr4_Update	Updater for DR4 register.
ADC_dr5	Register DR5: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.
ADC_dr5_Get	DR5: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.
ADC_dr5_Update	Updater for DR5 register.
ADC_dr6	Register DR6: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.
ADC_dr6_Get	DR6: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.
ADC_dr6_Update	Updater for DR6 register.
ADC_dr7	Register DR7: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.
ADC_dr7_Get	DR7: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.
ADC_dr7_Update	Updater for DR7 register.
ADC_gdr	Register GDR: A/D Global Data Register. Contains the result of the most recent A/D conversion.
ADC_gdr_Get	GDR: A/D Global Data Register. Contains the result of the most recent A/D conversion.
ADC_gdr_Update	Updater for GDR register.
ADC_inten	Register INTEN: A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.
ADC_inten_Get	INTEN: A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.
ADC_inten_Update	Updater for INTEN register.
ADC_stat	Register STAT: A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag.
ADC_stat_Get	STAT: A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag.
CT16B0	Product name title=UM10398 Chapter title=LPC1100XL series: 16-bit counter/timer CT16B0/1 Modification date=2/22/2012 Major revision=8 Minor revision=not available
CT16B0_ccr	Register CCR: Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
CT16B0_ccr_Get	CCR: Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
CT16B0_ccr_Update	Updater for CCR register.
CT16B0_cr0	Register CR0: Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.
CT16B0_cr0_Get	CR0: Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.
CT16B0_cr1	Register CR1: Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.
CT16B0_cr1_Get	CR1: Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.
CT16B0_ctcr	Register CTCR: Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
CT16B0_ctcr_Get	CTCR: Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
CT16B0_ctcr_Update	Updater for CTCR register.
CT16B0_emr	Register EMR: External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT[2:0].
CT16B0_emr_Get	EMR: External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT[2:0].
CT16B0_emr_Update	Updater for EMR register.
CT16B0_ir	Register IR: Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.
CT16B0_ir_Get	IR: Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.
CT16B0_ir_Update	Updater for IR register.
CT16B0_mcr	Register MCR: Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
CT16B0_mcr_Get	MCR: Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
CT16B0_mcr_Update	Updater for MCR register.
CT16B0_mr0	Register MR0: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
CT16B0_mr0_Get	MR0: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
CT16B0_mr0_Update	Updater for MR0 register.
CT16B0_mr1	Register MR1: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
CT16B0_mr1_Get	MR1: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
CT16B0_mr1_Update	Updater for MR1 register.
CT16B0_mr2	Register MR2: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
CT16B0_mr2_Get	MR2: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
CT16B0_mr2_Update	Updater for MR2 register.
CT16B0_mr3	Register MR3: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
CT16B0_mr3_Get	MR3: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
CT16B0_mr3_Update	Updater for MR3 register.
CT16B0_pc	Register PC: Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
CT16B0_pc_Get	PC: Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
CT16B0_pc_Update	Updater for PC register.
CT16B0_pr	Register PR: Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.
CT16B0_pr_Get	PR: Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.
CT16B0_pr_Update	Updater for PR register.
CT16B0_pwmc	Register PWMC: PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT[2:0].
CT16B0_pwmc_Get	PWMC: PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT[2:0].
CT16B0_pwmc_Update	Updater for PWMC register.
CT16B0_tc	Register TC: Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
CT16B0_tc_Get	TC: Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
CT16B0_tc_Update	Updater for TC register.
CT16B0_tcr	Register TCR: Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
CT16B0_tcr_Get	TCR: Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
CT16B0_tcr_Update	Updater for TCR register.
CT16B1	LPC11xx, LPC11Cxx, LPC11xxL, LPC11xxXL
CT32B0	Product name title=UM10398 Chapter title=LPC1100XL series: 32-bit counter/timer CT32B0/1 Modification date=2/22/2012 Major revision=8 Minor revision=not available
CT32B0_ccr	Register CCR: Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
CT32B0_ccr_Get	CCR: Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
CT32B0_ccr_Update	Updater for CCR register.
CT32B0_cr0	Register CR0: Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.
CT32B0_cr0_Get	CR0: Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.
CT32B0_cr1	Register CR1: Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.
CT32B0_cr1_Get	CR1: Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.
CT32B0_ctcr	Register CTCR: Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
CT32B0_ctcr_Get	CTCR: Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
CT32B0_ctcr_Update	Updater for CTCR register.
CT32B0_emr	Register EMR: External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0].
CT32B0_emr_Get	EMR: External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0].
CT32B0_emr_Update	Updater for EMR register.
CT32B0_ir	Register IR: Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.
CT32B0_ir_Get	IR: Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.
CT32B0_ir_Update	Updater for IR register.
CT32B0_mcr	Register MCR: Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
CT32B0_mcr_Get	MCR: Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
CT32B0_mcr_Update	Updater for MCR register.
CT32B0_mr0	Register MR0: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
CT32B0_mr0_Get	MR0: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
CT32B0_mr0_Update	Updater for MR0 register.
CT32B0_mr1	Register MR1: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
CT32B0_mr1_Get	MR1: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
CT32B0_mr1_Update	Updater for MR1 register.
CT32B0_mr2	Register MR2: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
CT32B0_mr2_Get	MR2: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
CT32B0_mr2_Update	Updater for MR2 register.
CT32B0_mr3	Register MR3: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
CT32B0_mr3_Get	MR3: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
CT32B0_mr3_Update	Updater for MR3 register.
CT32B0_pc	Register PC: Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
CT32B0_pc_Get	PC: Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
CT32B0_pc_Update	Updater for PC register.
CT32B0_pr	Register PR: Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.
CT32B0_pr_Get	PR: Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.
CT32B0_pr_Update	Updater for PR register.
CT32B0_pwmc	Register PWMC: PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0].
CT32B0_pwmc_Get	PWMC: PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0].
CT32B0_pwmc_Update	Updater for PWMC register.
CT32B0_tc	Register TC: Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
CT32B0_tc_Get	TC: Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
CT32B0_tc_Update	Updater for TC register.
CT32B0_tcr	Register TCR: Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
CT32B0_tcr_Get	TCR: Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
CT32B0_tcr_Update	Updater for TCR register.
CT32B1	LPC11xx, LPC11Cxx, LPC11xxL, LPC11xxXL
C_CAN	Product name title=UM10398 Chapter title=LPC111x/LPC11Cxx C_CAN controller Modification date=9/19/2011 Major revision=7 Minor revision=not available
C_CAN_canbrpe	Register CANBRPE: Baud rate prescaler extension register
C_CAN_canbrpe_Get	CANBRPE: Baud rate prescaler extension register
C_CAN_canbrpe_Update	Updater for CANBRPE register.
C_CAN_canbt	Register CANBT: Bit timing register
C_CAN_canbt_Get	CANBT: Bit timing register
C_CAN_canbt_Update	Updater for CANBT register.
C_CAN_canclkdiv	Register CANCLKDIV: Can clock divider register
C_CAN_canclkdiv_Get	CANCLKDIV: Can clock divider register
C_CAN_canclkdiv_Update	Updater for CANCLKDIV register.
C_CAN_cancntl	Register CANCNTL: CAN control
C_CAN_cancntl_Get	CANCNTL: CAN control
C_CAN_cancntl_Update	Updater for CANCNTL register.
C_CAN_canec	Register CANEC: Error counter
C_CAN_canec_Get	CANEC: Error counter
C_CAN_canif1_arb1	Register CANIF1_ARB1: Message interface 1 arbitration 1
C_CAN_canif1_arb1_Get	CANIF1_ARB1: Message interface 1 arbitration 1
C_CAN_canif1_arb1_Update	Updater for CANIF1_ARB1 register.
C_CAN_canif1_arb2	Register CANIF1_ARB2: Message interface 1 arbitration 2
C_CAN_canif1_arb2_Get	CANIF1_ARB2: Message interface 1 arbitration 2
C_CAN_canif1_arb2_Update	Updater for CANIF1_ARB2 register.
C_CAN_canif1_cmdmsk_r	Register CANIF1_CMDMSK_R: Message interface command mask - read direction
C_CAN_canif1_cmdmsk_r_Get	CANIF1_CMDMSK_R: Message interface command mask - read direction
C_CAN_canif1_cmdmsk_r_Update	Updater for CANIF1_CMDMSK_R register.
C_CAN_canif1_cmdmsk_w	Register CANIF1_CMDMSK_W: Message interface command mask - write direction
C_CAN_canif1_cmdmsk_w_Get	CANIF1_CMDMSK_W: Message interface command mask - write direction
C_CAN_canif1_cmdmsk_w_Update	Updater for CANIF1_CMDMSK_W register.
C_CAN_canif1_cmdreq	Register CANIF1_CMDREQ: Message interface command request
C_CAN_canif1_cmdreq_Get	CANIF1_CMDREQ: Message interface command request
C_CAN_canif1_cmdreq_Update	Updater for CANIF1_CMDREQ register.
C_CAN_canif1_da1	Register CANIF1_DA1: Message interface 1 data A1
C_CAN_canif1_da1_Get	CANIF1_DA1: Message interface 1 data A1
C_CAN_canif1_da1_Update	Updater for CANIF1_DA1 register.
C_CAN_canif1_da2	Register CANIF1_DA2: Message interface 1 data A2
C_CAN_canif1_da2_Get	CANIF1_DA2: Message interface 1 data A2
C_CAN_canif1_da2_Update	Updater for CANIF1_DA2 register.
C_CAN_canif1_db1	Register CANIF1_DB1: Message interface 1 data B1
C_CAN_canif1_db1_Get	CANIF1_DB1: Message interface 1 data B1
C_CAN_canif1_db1_Update	Updater for CANIF1_DB1 register.
C_CAN_canif1_db2	Register CANIF1_DB2: Message interface 1 data B2
C_CAN_canif1_db2_Get	CANIF1_DB2: Message interface 1 data B2
C_CAN_canif1_db2_Update	Updater for CANIF1_DB2 register.
C_CAN_canif1_mctrl	Register CANIF1_MCTRL: Message interface 1 message control
C_CAN_canif1_mctrl_Get	CANIF1_MCTRL: Message interface 1 message control
C_CAN_canif1_mctrl_Update	Updater for CANIF1_MCTRL register.
C_CAN_canif1_msk1	Register CANIF1_MSK1: Message interface 1 mask 1
C_CAN_canif1_msk1_Get	CANIF1_MSK1: Message interface 1 mask 1
C_CAN_canif1_msk1_Update	Updater for CANIF1_MSK1 register.
C_CAN_canif1_msk2	Register CANIF1_MSK2: Message interface 1 mask 2
C_CAN_canif1_msk2_Get	CANIF1_MSK2: Message interface 1 mask 2
C_CAN_canif1_msk2_Update	Updater for CANIF1_MSK2 register.
C_CAN_canif2_arb1	Register CANIF2_ARB1: Message interface 1 arbitration 1
C_CAN_canif2_arb1_Get	CANIF2_ARB1: Message interface 1 arbitration 1
C_CAN_canif2_arb1_Update	Updater for CANIF2_ARB1 register.
C_CAN_canif2_arb2	Register CANIF2_ARB2: Message interface 1 arbitration 2
C_CAN_canif2_arb2_Get	CANIF2_ARB2: Message interface 1 arbitration 2
C_CAN_canif2_arb2_Update	Updater for CANIF2_ARB2 register.
C_CAN_canif2_cmdmsk_r	Register CANIF2_CMDMSK_R: Message interface command mask - read direction
C_CAN_canif2_cmdmsk_r_Get	CANIF2_CMDMSK_R: Message interface command mask - read direction
C_CAN_canif2_cmdmsk_r_Update	Updater for CANIF2_CMDMSK_R register.
C_CAN_canif2_cmdmsk_w	Register CANIF2_CMDMSK_W: Message interface command mask - write direction
C_CAN_canif2_cmdmsk_w_Get	CANIF2_CMDMSK_W: Message interface command mask - write direction
C_CAN_canif2_cmdmsk_w_Update	Updater for CANIF2_CMDMSK_W register.
C_CAN_canif2_cmdreq	Register CANIF2_CMDREQ: Message interface command request
C_CAN_canif2_cmdreq_Get	CANIF2_CMDREQ: Message interface command request
C_CAN_canif2_cmdreq_Update	Updater for CANIF2_CMDREQ register.
C_CAN_canif2_da1	Register CANIF2_DA1: Message interface 1 data A1
C_CAN_canif2_da1_Get	CANIF2_DA1: Message interface 1 data A1
C_CAN_canif2_da1_Update	Updater for CANIF2_DA1 register.
C_CAN_canif2_da2	Register CANIF2_DA2: Message interface 1 data A2
C_CAN_canif2_da2_Get	CANIF2_DA2: Message interface 1 data A2
C_CAN_canif2_da2_Update	Updater for CANIF2_DA2 register.
C_CAN_canif2_db1	Register CANIF2_DB1: Message interface 1 data B1
C_CAN_canif2_db1_Get	CANIF2_DB1: Message interface 1 data B1
C_CAN_canif2_db1_Update	Updater for CANIF2_DB1 register.
C_CAN_canif2_db2	Register CANIF2_DB2: Message interface 1 data B2
C_CAN_canif2_db2_Get	CANIF2_DB2: Message interface 1 data B2
C_CAN_canif2_db2_Update	Updater for CANIF2_DB2 register.
C_CAN_canif2_mctrl	Register CANIF2_MCTRL: Message interface 1 message control
C_CAN_canif2_mctrl_Get	CANIF2_MCTRL: Message interface 1 message control
C_CAN_canif2_mctrl_Update	Updater for CANIF2_MCTRL register.
C_CAN_canif2_msk1	Register CANIF2_MSK1: Message interface 1 mask 1
C_CAN_canif2_msk1_Get	CANIF2_MSK1: Message interface 1 mask 1
C_CAN_canif2_msk1_Update	Updater for CANIF2_MSK1 register.
C_CAN_canif2_msk2	Register CANIF2_MSK2: Message interface 1 mask 2
C_CAN_canif2_msk2_Get	CANIF2_MSK2: Message interface 1 mask 2
C_CAN_canif2_msk2_Update	Updater for CANIF2_MSK2 register.
C_CAN_canint	Register CANINT: Interrupt register
C_CAN_canint_Get	CANINT: Interrupt register
C_CAN_canir1	Register CANIR1: Interrupt pending 1
C_CAN_canir1_Get	CANIR1: Interrupt pending 1
C_CAN_canir2	Register CANIR2: Interrupt pending 2
C_CAN_canir2_Get	CANIR2: Interrupt pending 2
C_CAN_canmsgv1	Register CANMSGV1: Message valid 1
C_CAN_canmsgv1_Get	CANMSGV1: Message valid 1
C_CAN_canmsgv2	Register CANMSGV2: Message valid 2
C_CAN_canmsgv2_Get	CANMSGV2: Message valid 2
C_CAN_cannd1	Register CANND1: New data 1
C_CAN_cannd1_Get	CANND1: New data 1
C_CAN_cannd2	Register CANND2: New data 2
C_CAN_cannd2_Get	CANND2: New data 2
C_CAN_canstat	Register CANSTAT: Status register
C_CAN_canstat_Get	CANSTAT: Status register
C_CAN_canstat_Update	Updater for CANSTAT register.
C_CAN_cantest	Register CANTEST: Test register
C_CAN_cantest_Get	CANTEST: Test register
C_CAN_cantest_Update	Updater for CANTEST register.
C_CAN_cantxreq1	Register CANTXREQ1: Transmission request 1
C_CAN_cantxreq1_Get	CANTXREQ1: Transmission request 1
C_CAN_cantxreq2	Register CANTXREQ2: Transmission request 2
C_CAN_cantxreq2_Get	CANTXREQ2: Transmission request 2
FLASHCTRL	Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3
FLASHCTRL_flashcfg	Register FLASHCFG: Flash memory access time configuration register
FLASHCTRL_flashcfg_Get	FLASHCFG: Flash memory access time configuration register
FLASHCTRL_flashcfg_Update	Updater for FLASHCFG register.
FLASHCTRL_fmsstart	Register FMSSTART: Signature start address register
FLASHCTRL_fmsstart_Get	FMSSTART: Signature start address register
FLASHCTRL_fmsstart_Update	Updater for FMSSTART register.
FLASHCTRL_fmsstop	Register FMSSTOP: Signature stop-address register
FLASHCTRL_fmsstop_Get	FMSSTOP: Signature stop-address register
FLASHCTRL_fmsstop_Update	Updater for FMSSTOP register.
FLASHCTRL_fmstat	Register FMSTAT: Signature generation status register
FLASHCTRL_fmstat_Get	FMSTAT: Signature generation status register
FLASHCTRL_fmstatclr	Register FMSTATCLR: Signature generation status clear register
FLASHCTRL_fmstatclr_Update	Updater for FMSTATCLR register.
FLASHCTRL_fmsw0	Register FMSW0: Word 0 [31:0]
FLASHCTRL_fmsw0_Get	FMSW0: Word 0 [31:0]
FLASHCTRL_fmsw1	Register FMSW1: Word 1 [63:32]
FLASHCTRL_fmsw1_Get	FMSW1: Word 1 [63:32]
FLASHCTRL_fmsw2	Register FMSW2: Word 2 [95:64]
FLASHCTRL_fmsw2_Get	FMSW2: Word 2 [95:64]
FLASHCTRL_fmsw3	Register FMSW3: Word 3 [127:96]
FLASHCTRL_fmsw3_Get	FMSW3: Word 3 [127:96]
GPIO0	GPIO0
GPIO0_data	Register DATA: Port n data register for pins PIOn_0 to PIOn_11
GPIO0_data_Get	DATA: Port n data register for pins PIOn_0 to PIOn_11
GPIO0_data_Update	Updater for DATA register.
GPIO0_dir	Register DIR: Data direction register for port n
GPIO0_dir_Get	DIR: Data direction register for port n
GPIO0_dir_Update	Updater for DIR register.
GPIO0_ibe	Register IBE: Interrupt both edges register for port n
GPIO0_ibe_Get	IBE: Interrupt both edges register for port n
GPIO0_ibe_Update	Updater for IBE register.
GPIO0_ic	Register IC: Interrupt clear register for port n
GPIO0_ic_Update	Updater for IC register.
GPIO0_ie	Register IE: Interrupt mask register for port n
GPIO0_ie_Get	IE: Interrupt mask register for port n
GPIO0_ie_Update	Updater for IE register.
GPIO0_iev	Register IEV: Interrupt event register for port n
GPIO0_iev_Get	IEV: Interrupt event register for port n
GPIO0_iev_Update	Updater for IEV register.
GPIO0_is	Register IS: Interrupt sense register for port n
GPIO0_is_Get	IS: Interrupt sense register for port n
GPIO0_is_Update	Updater for IS register.
GPIO0_mis	Register MIS: Masked interrupt status register for port n
GPIO0_mis_Get	MIS: Masked interrupt status register for port n
GPIO0_ris	Register RIS: Raw interrupt status register for port n
GPIO0_ris_Get	RIS: Raw interrupt status register for port n
GPIO1	LPC11xx, LPC11Cxx, LPC11xxL, LPC11xxXL
GPIO2	LPC11xx, LPC11Cxx, LPC11xxL, LPC11xxXL
GPIO3	LPC11xx, LPC11Cxx, LPC11xxL, LPC11xxXL
I2C	I2C
I2C_adr0	Register ADR0: I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.
I2C_adr0_Get	ADR0: I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.
I2C_adr0_Update	Updater for ADR0 register.
I2C_adr1	Register ADR1: I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.
I2C_adr1_Get	ADR1: I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.
I2C_adr1_Update	Updater for ADR1 register.
I2C_adr2	Register ADR2: I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.
I2C_adr2_Get	ADR2: I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.
I2C_adr2_Update	Updater for ADR2 register.
I2C_adr3	Register ADR3: I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.
I2C_adr3_Get	ADR3: I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.
I2C_adr3_Update	Updater for ADR3 register.
I2C_conclr	Register CONCLR: I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.
I2C_conclr_Update	Updater for CONCLR register.
I2C_conset	Register CONSET: I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.
I2C_conset_Get	CONSET: I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.
I2C_conset_Update	Updater for CONSET register.
I2C_dat	Register DAT: I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.
I2C_dat_Get	DAT: I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.
I2C_dat_Update	Updater for DAT register.
I2C_data_buffer	Register DATA_BUFFER: Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.
I2C_data_buffer_Get	DATA_BUFFER: Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.
I2C_mask0	Register MASK0: I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).
I2C_mask0_Get	MASK0: I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).
I2C_mask0_Update	Updater for MASK0 register.
I2C_mask1	Register MASK1: I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).
I2C_mask1_Get	MASK1: I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).
I2C_mask1_Update	Updater for MASK1 register.
I2C_mask2	Register MASK2: I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).
I2C_mask2_Get	MASK2: I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).
I2C_mask2_Update	Updater for MASK2 register.
I2C_mask3	Register MASK3: I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).
I2C_mask3_Get	MASK3: I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).
I2C_mask3_Update	Updater for MASK3 register.
I2C_mmctrl	Register MMCTRL: Monitor mode control register.
I2C_mmctrl_Get	MMCTRL: Monitor mode control register.
I2C_mmctrl_Update	Updater for MMCTRL register.
I2C_sclh	Register SCLH: SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.
I2C_sclh_Get	SCLH: SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.
I2C_sclh_Update	Updater for SCLH register.
I2C_scll	Register SCLL: SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.
I2C_scll_Get	SCLL: SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.
I2C_scll_Update	Updater for SCLL register.
I2C_stat	Register STAT: I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.
I2C_stat_Get	STAT: I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.
IOCON	Product name title=UM10398 Chapter title=LPC1100XL series: I/O configuration (IOCONFIG) Modification date=2/22/2012 Major revision=8 Minor revision=not available
IOCON_iocon_ct16b0_cap0_loc	Register IOCON_CT16B0_CAP0_LOC: CT16B0_CAP0 pin location select register
IOCON_iocon_ct16b0_cap0_loc_Get	IOCON_CT16B0_CAP0_LOC: CT16B0_CAP0 pin location select register
IOCON_iocon_ct16b0_cap0_loc_Update	Updater for IOCON_CT16B0_CAP0_LOC register.
IOCON_iocon_ct32b0_cap0_loc	Register IOCON_CT32B0_CAP0_LOC: CT32B0_CAP0 pin location select register
IOCON_iocon_ct32b0_cap0_loc_Get	IOCON_CT32B0_CAP0_LOC: CT32B0_CAP0 pin location select register
IOCON_iocon_ct32b0_cap0_loc_Update	Updater for IOCON_CT32B0_CAP0_LOC register.
IOCON_iocon_dcd_loc	Register IOCON_DCD_LOC: DCD pin location select register
IOCON_iocon_dcd_loc_Get	IOCON_DCD_LOC: DCD pin location select register
IOCON_iocon_dcd_loc_Update	Updater for IOCON_DCD_LOC register.
IOCON_iocon_dsr_loc	Register IOCON_DSR_LOC: DSR pin location select register
IOCON_iocon_dsr_loc_Get	IOCON_DSR_LOC: DSR pin location select register
IOCON_iocon_dsr_loc_Update	Updater for IOCON_DSR_LOC register.
IOCON_iocon_miso1_loc	Register IOCON_MISO1_LOC: MISO1 pin location select register
IOCON_iocon_miso1_loc_Get	IOCON_MISO1_LOC: MISO1 pin location select register
IOCON_iocon_miso1_loc_Update	Updater for IOCON_MISO1_LOC register.
IOCON_iocon_mosi1_loc	Register IOCON_MOSI1_LOC: MOSI1 pin location select register
IOCON_iocon_mosi1_loc_Get	IOCON_MOSI1_LOC: MOSI1 pin location select register
IOCON_iocon_mosi1_loc_Update	Updater for IOCON_MOSI1_LOC register.
IOCON_iocon_pio0_1	Register IOCON_PIO0_1: I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2
IOCON_iocon_pio0_1_Get	IOCON_PIO0_1: I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2
IOCON_iocon_pio0_1_Update	Updater for IOCON_PIO0_1 register.
IOCON_iocon_pio0_2	Register IOCON_PIO0_2: I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0
IOCON_iocon_pio0_2_Get	IOCON_PIO0_2: I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0
IOCON_iocon_pio0_2_Update	Updater for IOCON_PIO0_2 register.
IOCON_iocon_pio0_3	Register IOCON_PIO0_3: I/O configuration for pin PIO0_3
IOCON_iocon_pio0_3_Get	IOCON_PIO0_3: I/O configuration for pin PIO0_3
IOCON_iocon_pio0_3_Update	Updater for IOCON_PIO0_3 register.
IOCON_iocon_pio0_4	Register IOCON_PIO0_4: I/O configuration for pin PIO0_4/SCL
IOCON_iocon_pio0_4_Get	IOCON_PIO0_4: I/O configuration for pin PIO0_4/SCL
IOCON_iocon_pio0_4_Update	Updater for IOCON_PIO0_4 register.
IOCON_iocon_pio0_5	Register IOCON_PIO0_5: I/O configuration for pin PIO0_5/SDA
IOCON_iocon_pio0_5_Get	IOCON_PIO0_5: I/O configuration for pin PIO0_5/SDA
IOCON_iocon_pio0_5_Update	Updater for IOCON_PIO0_5 register.
IOCON_iocon_pio0_6	Register IOCON_PIO0_6: I/O configuration for pin PIO0_6/SCK0
IOCON_iocon_pio0_6_Get	IOCON_PIO0_6: I/O configuration for pin PIO0_6/SCK0
IOCON_iocon_pio0_6_Update	Updater for IOCON_PIO0_6 register.
IOCON_iocon_pio0_7	Register IOCON_PIO0_7: I/O configuration for pin PIO0_7/CTS
IOCON_iocon_pio0_7_Get	IOCON_PIO0_7: I/O configuration for pin PIO0_7/CTS
IOCON_iocon_pio0_7_Update	Updater for IOCON_PIO0_7 register.
IOCON_iocon_pio0_8	Register IOCON_PIO0_8: I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0
IOCON_iocon_pio0_8_Get	IOCON_PIO0_8: I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0
IOCON_iocon_pio0_8_Update	Updater for IOCON_PIO0_8 register.
IOCON_iocon_pio0_9	Register IOCON_PIO0_9: I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1
IOCON_iocon_pio0_9_Get	IOCON_PIO0_9: I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1
IOCON_iocon_pio0_9_Update	Updater for IOCON_PIO0_9 register.
IOCON_iocon_pio1_10	Register IOCON_PIO1_10: I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1/ MISO1
IOCON_iocon_pio1_10_Get	IOCON_PIO1_10: I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1/ MISO1
IOCON_iocon_pio1_10_Update	Updater for IOCON_PIO1_10 register.
IOCON_iocon_pio1_11	Register IOCON_PIO1_11: I/O configuration for pin PIO1_11/AD7/CT32B1_CAP1
IOCON_iocon_pio1_11_Get	IOCON_PIO1_11: I/O configuration for pin PIO1_11/AD7/CT32B1_CAP1
IOCON_iocon_pio1_11_Update	Updater for IOCON_PIO1_11 register.
IOCON_iocon_pio1_4	Register IOCON_PIO1_4: I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3
IOCON_iocon_pio1_4_Get	IOCON_PIO1_4: I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3
IOCON_iocon_pio1_4_Update	Updater for IOCON_PIO1_4 register.
IOCON_iocon_pio1_5	Register IOCON_PIO1_5: I/O configuration for pin PIO1_5/RTS/CT32B0_CAP0
IOCON_iocon_pio1_5_Get	IOCON_PIO1_5: I/O configuration for pin PIO1_5/RTS/CT32B0_CAP0
IOCON_iocon_pio1_5_Update	Updater for IOCON_PIO1_5 register.
IOCON_iocon_pio1_6	Register IOCON_PIO1_6: I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0
IOCON_iocon_pio1_6_Get	IOCON_PIO1_6: I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0
IOCON_iocon_pio1_6_Update	Updater for IOCON_PIO1_6 register.
IOCON_iocon_pio1_7	Register IOCON_PIO1_7: I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1
IOCON_iocon_pio1_7_Get	IOCON_PIO1_7: I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1
IOCON_iocon_pio1_7_Update	Updater for IOCON_PIO1_7 register.
IOCON_iocon_pio1_8	Register IOCON_PIO1_8: I/O configuration for pin PIO1_8/CT16B1_CAP0
IOCON_iocon_pio1_8_Get	IOCON_PIO1_8: I/O configuration for pin PIO1_8/CT16B1_CAP0
IOCON_iocon_pio1_8_Update	Updater for IOCON_PIO1_8 register.
IOCON_iocon_pio1_9	Register IOCON_PIO1_9: I/O configuration for pin PIO1_9/CT16B1_MAT0/ MOSI1
IOCON_iocon_pio1_9_Get	IOCON_PIO1_9: I/O configuration for pin PIO1_9/CT16B1_MAT0/ MOSI1
IOCON_iocon_pio1_9_Update	Updater for IOCON_PIO1_9 register.
IOCON_iocon_pio2_0	Register IOCON_PIO2_0: I/O configuration for pin PIO2_0/DTR/SSEL1
IOCON_iocon_pio2_0_Get	IOCON_PIO2_0: I/O configuration for pin PIO2_0/DTR/SSEL1
IOCON_iocon_pio2_0_Update	Updater for IOCON_PIO2_0 register.
IOCON_iocon_pio2_1	Register IOCON_PIO2_1: I/O configuration for pin PIO2_1/DSR/SCK1
IOCON_iocon_pio2_10	Register IOCON_PIO2_10: I/O configuration for pin PIO2_10
IOCON_iocon_pio2_10_Get	IOCON_PIO2_10: I/O configuration for pin PIO2_10
IOCON_iocon_pio2_10_Update	Updater for IOCON_PIO2_10 register.
IOCON_iocon_pio2_11	Register IOCON_PIO2_11: I/O configuration for pin PIO2_11/SCK0/ CT32B0_CAP1
IOCON_iocon_pio2_11_Get	IOCON_PIO2_11: I/O configuration for pin PIO2_11/SCK0/ CT32B0_CAP1
IOCON_iocon_pio2_11_Update	Updater for IOCON_PIO2_11 register.
IOCON_iocon_pio2_1_Get	IOCON_PIO2_1: I/O configuration for pin PIO2_1/DSR/SCK1
IOCON_iocon_pio2_1_Update	Updater for IOCON_PIO2_1 register.
IOCON_iocon_pio2_2	Register IOCON_PIO2_2: I/O configuration for pin PIO2_2/DCD/MISO1
IOCON_iocon_pio2_2_Get	IOCON_PIO2_2: I/O configuration for pin PIO2_2/DCD/MISO1
IOCON_iocon_pio2_2_Update	Updater for IOCON_PIO2_2 register.
IOCON_iocon_pio2_3	Register IOCON_PIO2_3: I/O configuration for pin PIO2_3/RI/MOSI1
IOCON_iocon_pio2_3_Get	IOCON_PIO2_3: I/O configuration for pin PIO2_3/RI/MOSI1
IOCON_iocon_pio2_3_Update	Updater for IOCON_PIO2_3 register.
IOCON_iocon_pio2_4	Register IOCON_PIO2_4: I/O configuration for pin PIO2_4/ CT16B1_MAT1/ SSEL1
IOCON_iocon_pio2_4_Get	IOCON_PIO2_4: I/O configuration for pin PIO2_4/ CT16B1_MAT1/ SSEL1
IOCON_iocon_pio2_4_Update	Updater for IOCON_PIO2_4 register.
IOCON_iocon_pio2_5	Register IOCON_PIO2_5: I/O configuration for pin PIO2_5/ CT32B0_MAT0
IOCON_iocon_pio2_5_Get	IOCON_PIO2_5: I/O configuration for pin PIO2_5/ CT32B0_MAT0
IOCON_iocon_pio2_5_Update	Updater for IOCON_PIO2_5 register.
IOCON_iocon_pio2_6	Register IOCON_PIO2_6: I/O configuration for pin PIO2_6/ CT32B0_MAT1
IOCON_iocon_pio2_6_Get	IOCON_PIO2_6: I/O configuration for pin PIO2_6/ CT32B0_MAT1
IOCON_iocon_pio2_6_Update	Updater for IOCON_PIO2_6 register.
IOCON_iocon_pio2_7	Register IOCON_PIO2_7: I/O configuration for pin PIO2_7/ CT32B0_MAT2/RXD
IOCON_iocon_pio2_7_Get	IOCON_PIO2_7: I/O configuration for pin PIO2_7/ CT32B0_MAT2/RXD
IOCON_iocon_pio2_7_Update	Updater for IOCON_PIO2_7 register.
IOCON_iocon_pio2_8	Register IOCON_PIO2_8: I/O configuration for pin PIO2_8/ CT32B0_MAT3/TXD
IOCON_iocon_pio2_8_Get	IOCON_PIO2_8: I/O configuration for pin PIO2_8/ CT32B0_MAT3/TXD
IOCON_iocon_pio2_8_Update	Updater for IOCON_PIO2_8 register.
IOCON_iocon_pio2_9	Register IOCON_PIO2_9: I/O configuration for pin PIO2_9/ CT32B0_CAP0
IOCON_iocon_pio2_9_Get	IOCON_PIO2_9: I/O configuration for pin PIO2_9/ CT32B0_CAP0
IOCON_iocon_pio2_9_Update	Updater for IOCON_PIO2_9 register.
IOCON_iocon_pio3_0	Register IOCON_PIO3_0: I/O configuration for pin PIO3_0/DTR/CT16B0_MAT0/TXD
IOCON_iocon_pio3_0_Get	IOCON_PIO3_0: I/O configuration for pin PIO3_0/DTR/CT16B0_MAT0/TXD
IOCON_iocon_pio3_0_Update	Updater for IOCON_PIO3_0 register.
IOCON_iocon_pio3_1	Register IOCON_PIO3_1: I/O configuration for pin PIO3_1/DSR/CT16B0_MAT1/RXD
IOCON_iocon_pio3_1_Get	IOCON_PIO3_1: I/O configuration for pin PIO3_1/DSR/CT16B0_MAT1/RXD
IOCON_iocon_pio3_1_Update	Updater for IOCON_PIO3_1 register.
IOCON_iocon_pio3_2	Register IOCON_PIO3_2: I/O configuration for pin PIO3_2/DCD/ CT16B0_MAT2/SCK1
IOCON_iocon_pio3_2_Get	IOCON_PIO3_2: I/O configuration for pin PIO3_2/DCD/ CT16B0_MAT2/SCK1
IOCON_iocon_pio3_2_Update	Updater for IOCON_PIO3_2 register.
IOCON_iocon_pio3_3	Register IOCON_PIO3_3: I/O configuration for pin PIO3_3/RI/ CT16B0_CAP0
IOCON_iocon_pio3_3_Get	IOCON_PIO3_3: I/O configuration for pin PIO3_3/RI/ CT16B0_CAP0
IOCON_iocon_pio3_3_Update	Updater for IOCON_PIO3_3 register.
IOCON_iocon_pio3_4	Register IOCON_PIO3_4: I/O configuration for pin PIO3_4/ CT16B0_CAP1/RXD
IOCON_iocon_pio3_4_Get	IOCON_PIO3_4: I/O configuration for pin PIO3_4/ CT16B0_CAP1/RXD
IOCON_iocon_pio3_4_Update	Updater for IOCON_PIO3_4 register.
IOCON_iocon_pio3_5	Register IOCON_PIO3_5: I/O configuration for pin PIO3_5/ CT16B1_CAP1/TXD
IOCON_iocon_pio3_5_Get	IOCON_PIO3_5: I/O configuration for pin PIO3_5/ CT16B1_CAP1/TXD
IOCON_iocon_pio3_5_Update	Updater for IOCON_PIO3_5 register.
IOCON_iocon_r_pio0_11	Register IOCON_R_PIO0_11: I/O configuration for pin R/PIO0_11/AD0/CT32B0_MAT3
IOCON_iocon_r_pio0_11_Get	IOCON_R_PIO0_11: I/O configuration for pin R/PIO0_11/AD0/CT32B0_MAT3
IOCON_iocon_r_pio0_11_Update	Updater for IOCON_R_PIO0_11 register.
IOCON_iocon_r_pio1_0	Register IOCON_R_PIO1_0: I/O configuration for pin R/PIO1_0/AD1/CT32B1_CAP0
IOCON_iocon_r_pio1_0_Get	IOCON_R_PIO1_0: I/O configuration for pin R/PIO1_0/AD1/CT32B1_CAP0
IOCON_iocon_r_pio1_0_Update	Updater for IOCON_R_PIO1_0 register.
IOCON_iocon_r_pio1_1	Register IOCON_R_PIO1_1: I/O configuration for pin R/PIO1_1/AD2/CT32B1_MAT0
IOCON_iocon_r_pio1_1_Get	IOCON_R_PIO1_1: I/O configuration for pin R/PIO1_1/AD2/CT32B1_MAT0
IOCON_iocon_r_pio1_1_Update	Updater for IOCON_R_PIO1_1 register.
IOCON_iocon_r_pio1_2	Register IOCON_R_PIO1_2: I/O configuration for pin R/PIO1_2/AD3/CT32B1_MAT1
IOCON_iocon_r_pio1_2_Get	IOCON_R_PIO1_2: I/O configuration for pin R/PIO1_2/AD3/CT32B1_MAT1
IOCON_iocon_r_pio1_2_Update	Updater for IOCON_R_PIO1_2 register.
IOCON_iocon_reset_pio0_0	Register IOCON_RESET_PIO0_0: I/O configuration for pin RESET/PIO0_0
IOCON_iocon_reset_pio0_0_Get	IOCON_RESET_PIO0_0: I/O configuration for pin RESET/PIO0_0
IOCON_iocon_reset_pio0_0_Update	Updater for IOCON_RESET_PIO0_0 register.
IOCON_iocon_ri_loc	Register IOCON_RI_LOC: RI pin location select register
IOCON_iocon_ri_loc_Get	IOCON_RI_LOC: RI pin location select register
IOCON_iocon_ri_loc_Update	Updater for IOCON_RI_LOC register.
IOCON_iocon_rxd_loc	Register IOCON_RXD_LOC: RXD pin location select register
IOCON_iocon_rxd_loc_Get	IOCON_RXD_LOC: RXD pin location select register
IOCON_iocon_rxd_loc_Update	Updater for IOCON_RXD_LOC register.
IOCON_iocon_sck0_loc	Register IOCON_SCK0_LOC: SCK0 pin location select register
IOCON_iocon_sck0_loc_Get	IOCON_SCK0_LOC: SCK0 pin location select register
IOCON_iocon_sck0_loc_Update	Updater for IOCON_SCK0_LOC register.
IOCON_iocon_sck1_loc	Register IOCON_SCK1_LOC: SCK1 pin location select register
IOCON_iocon_sck1_loc_Get	IOCON_SCK1_LOC: SCK1 pin location select register
IOCON_iocon_sck1_loc_Update	Updater for IOCON_SCK1_LOC register.
IOCON_iocon_ssel1_loc	Register IOCON_SSEL1_LOC: SSEL1 pin location select register
IOCON_iocon_ssel1_loc_Get	IOCON_SSEL1_LOC: SSEL1 pin location select register
IOCON_iocon_ssel1_loc_Update	Updater for IOCON_SSEL1_LOC register.
IOCON_iocon_swclk_pio0_10	Register IOCON_SWCLK_PIO0_10: I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2
IOCON_iocon_swclk_pio0_10_Get	IOCON_SWCLK_PIO0_10: I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2
IOCON_iocon_swclk_pio0_10_Update	Updater for IOCON_SWCLK_PIO0_10 register.
IOCON_iocon_swdio_pio1_3	Register IOCON_SWDIO_PIO1_3: I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2
IOCON_iocon_swdio_pio1_3_Get	IOCON_SWDIO_PIO1_3: I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2
IOCON_iocon_swdio_pio1_3_Update	Updater for IOCON_SWDIO_PIO1_3 register.
PMU	power management unit
PMU_gpreg0	Register GPREG0: General purpose register
PMU_gpreg0_Get	GPREG0: General purpose register
PMU_gpreg0_Update	Updater for GPREG0 register.
PMU_gpreg1	Register GPREG1: General purpose register
PMU_gpreg1_Get	GPREG1: General purpose register
PMU_gpreg1_Update	Updater for GPREG1 register.
PMU_gpreg2	Register GPREG2: General purpose register
PMU_gpreg2_Get	GPREG2: General purpose register
PMU_gpreg2_Update	Updater for GPREG2 register.
PMU_gpreg3	Register GPREG3: General purpose register
PMU_gpreg3_Get	GPREG3: General purpose register
PMU_gpreg3_Update	Updater for GPREG3 register.
PMU_gpreg4	Register GPREG4: General purpose register 4
PMU_gpreg4_Get	GPREG4: General purpose register 4
PMU_gpreg4_Update	Updater for GPREG4 register.
PMU_pcon	Register PCON: Power control register
PMU_pcon_Get	PCON: Power control register
PMU_pcon_Update	Updater for PCON register.
SPI0	SPI0
SPI0_cpsr	Register CPSR: Clock Prescale Register
SPI0_cpsr_Get	CPSR: Clock Prescale Register
SPI0_cpsr_Update	Updater for CPSR register.
SPI0_cr0	Register CR0: Control Register 0. Selects the serial clock rate, bus type, and data size.
SPI0_cr0_Get	CR0: Control Register 0. Selects the serial clock rate, bus type, and data size.
SPI0_cr0_Update	Updater for CR0 register.
SPI0_cr1	Register CR1: Control Register 1. Selects master/slave and other modes.
SPI0_cr1_Get	CR1: Control Register 1. Selects master/slave and other modes.
SPI0_cr1_Update	Updater for CR1 register.
SPI0_dr	Register DR: Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.
SPI0_dr_Get	DR: Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.
SPI0_dr_Update	Updater for DR register.
SPI0_icr	Register ICR: SSPICR Interrupt Clear Register
SPI0_icr_Update	Updater for ICR register.
SPI0_imsc	Register IMSC: Interrupt Mask Set and Clear Register
SPI0_imsc_Get	IMSC: Interrupt Mask Set and Clear Register
SPI0_imsc_Update	Updater for IMSC register.
SPI0_mis	Register MIS: Masked Interrupt Status Register
SPI0_mis_Get	MIS: Masked Interrupt Status Register
SPI0_ris	Register RIS: Raw Interrupt Status Register
SPI0_ris_Get	RIS: Raw Interrupt Status Register
SPI0_sr	Register SR: Status Register
SPI0_sr_Get	SR: Status Register
SPI1	LPC11xx, LPC11Cxx, LPC11xxL, LPC11xxXL
SYSCON	Product name title=UM10398 Chapter title=LPC111x/LPC11Cxx System configuration (SYSCON) Modification date=2/22/2012 Major revision=8 Minor revision=not available
SYSCON_bodctrl	Register BODCTRL: BOD control
SYSCON_bodctrl_Get	BODCTRL: BOD control
SYSCON_bodctrl_Update	Updater for BODCTRL register.
SYSCON_clkoutclkdiv	Register CLKOUTCLKDIV: CLKOUT clock divider
SYSCON_clkoutclkdiv_Get	CLKOUTCLKDIV: CLKOUT clock divider
SYSCON_clkoutclkdiv_Update	Updater for CLKOUTCLKDIV register.
SYSCON_clkoutclksel	Register CLKOUTCLKSEL: CLKOUT clock source select
SYSCON_clkoutclksel_Get	CLKOUTCLKSEL: CLKOUT clock source select
SYSCON_clkoutclksel_Update	Updater for CLKOUTCLKSEL register.
SYSCON_clkoutuen	Register CLKOUTUEN: CLKOUT clock source update enable
SYSCON_clkoutuen_Get	CLKOUTUEN: CLKOUT clock source update enable
SYSCON_clkoutuen_Update	Updater for CLKOUTUEN register.
SYSCON_device_id	Register DEVICE_ID: Device ID register 0 for parts LPC1100, LPC1100C, LPC1100L.
SYSCON_device_id_Get	DEVICE_ID: Device ID register 0 for parts LPC1100, LPC1100C, LPC1100L.
SYSCON_ircctrl	Register IRCCTRL: IRC control
SYSCON_ircctrl_Get	IRCCTRL: IRC control
SYSCON_ircctrl_Update	Updater for IRCCTRL register.
SYSCON_mainclksel	Register MAINCLKSEL: Main clock source select
SYSCON_mainclksel_Get	MAINCLKSEL: Main clock source select
SYSCON_mainclksel_Update	Updater for MAINCLKSEL register.
SYSCON_mainclkuen	Register MAINCLKUEN: Main clock source update enable
SYSCON_mainclkuen_Get	MAINCLKUEN: Main clock source update enable
SYSCON_mainclkuen_Update	Updater for MAINCLKUEN register.
SYSCON_nmisrc	Register NMISRC: NMI source selection
SYSCON_nmisrc_Get	NMISRC: NMI source selection
SYSCON_nmisrc_Update	Updater for NMISRC register.
SYSCON_pdawakecfg	Register PDAWAKECFG: Power-down states after wake-up from Deep-sleep mode
SYSCON_pdawakecfg_Get	PDAWAKECFG: Power-down states after wake-up from Deep-sleep mode
SYSCON_pdawakecfg_Update	Updater for PDAWAKECFG register.
SYSCON_pdruncfg	Register PDRUNCFG: Power-down configuration register
SYSCON_pdruncfg_Get	PDRUNCFG: Power-down configuration register
SYSCON_pdruncfg_Update	Updater for PDRUNCFG register.
SYSCON_pdsleepcfg	Register PDSLEEPCFG: Power-down states in Deep-sleep mode
SYSCON_pdsleepcfg_Get	PDSLEEPCFG: Power-down states in Deep-sleep mode
SYSCON_pdsleepcfg_Update	Updater for PDSLEEPCFG register.
SYSCON_pioporcap0	Register PIOPORCAP0: POR captured PIO status 0
SYSCON_pioporcap0_Get	PIOPORCAP0: POR captured PIO status 0
SYSCON_pioporcap1	Register PIOPORCAP1: POR captured PIO status 1
SYSCON_pioporcap1_Get	PIOPORCAP1: POR captured PIO status 1
SYSCON_presetctrl	Register PRESETCTRL: Peripheral reset control
SYSCON_presetctrl_Get	PRESETCTRL: Peripheral reset control
SYSCON_presetctrl_Update	Updater for PRESETCTRL register.
SYSCON_ssp0clkdiv	Register SSP0CLKDIV: SPI0 clock divider
SYSCON_ssp0clkdiv_Get	SSP0CLKDIV: SPI0 clock divider
SYSCON_ssp0clkdiv_Update	Updater for SSP0CLKDIV register.
SYSCON_ssp1clkdiv	Register SSP1CLKDIV: SPI1 clock divder
SYSCON_ssp1clkdiv_Get	SSP1CLKDIV: SPI1 clock divder
SYSCON_ssp1clkdiv_Update	Updater for SSP1CLKDIV register.
SYSCON_startaprp0	Register STARTAPRP0: Start logic edge control register 0
SYSCON_startaprp0_Get	STARTAPRP0: Start logic edge control register 0
SYSCON_startaprp0_Update	Updater for STARTAPRP0 register.
SYSCON_starterp0	Register STARTERP0: Start logic signal enable register 0
SYSCON_starterp0_Get	STARTERP0: Start logic signal enable register 0
SYSCON_starterp0_Update	Updater for STARTERP0 register.
SYSCON_startrsrp0clr	Register STARTRSRP0CLR: Start logic reset register 0
SYSCON_startrsrp0clr_Update	Updater for STARTRSRP0CLR register.
SYSCON_startsrp0	Register STARTSRP0: Start logic status register 0
SYSCON_startsrp0_Get	STARTSRP0: Start logic status register 0
SYSCON_sysahbclkctrl	Register SYSAHBCLKCTRL: System AHB clock control
SYSCON_sysahbclkctrl_Get	SYSAHBCLKCTRL: System AHB clock control
SYSCON_sysahbclkctrl_Update	Updater for SYSAHBCLKCTRL register.
SYSCON_sysahbclkdiv	Register SYSAHBCLKDIV: System AHB clock divider
SYSCON_sysahbclkdiv_Get	SYSAHBCLKDIV: System AHB clock divider
SYSCON_sysahbclkdiv_Update	Updater for SYSAHBCLKDIV register.
SYSCON_sysmemremap	Register SYSMEMREMAP: System memory remap
SYSCON_sysmemremap_Get	SYSMEMREMAP: System memory remap
SYSCON_sysmemremap_Update	Updater for SYSMEMREMAP register.
SYSCON_sysoscctrl	Register SYSOSCCTRL: System oscillator control
SYSCON_sysoscctrl_Get	SYSOSCCTRL: System oscillator control
SYSCON_sysoscctrl_Update	Updater for SYSOSCCTRL register.
SYSCON_syspllclksel	Register SYSPLLCLKSEL: System PLL clock source select
SYSCON_syspllclksel_Get	SYSPLLCLKSEL: System PLL clock source select
SYSCON_syspllclksel_Update	Updater for SYSPLLCLKSEL register.
SYSCON_syspllclkuen	Register SYSPLLCLKUEN: System PLL clock source update enable
SYSCON_syspllclkuen_Get	SYSPLLCLKUEN: System PLL clock source update enable
SYSCON_syspllclkuen_Update	Updater for SYSPLLCLKUEN register.
SYSCON_syspllctrl	Register SYSPLLCTRL: System PLL control
SYSCON_syspllctrl_Get	SYSPLLCTRL: System PLL control
SYSCON_syspllctrl_Update	Updater for SYSPLLCTRL register.
SYSCON_syspllstat	Register SYSPLLSTAT: System PLL status
SYSCON_syspllstat_Get	SYSPLLSTAT: System PLL status
SYSCON_sysrststat	Register SYSRSTSTAT: System reset status register
SYSCON_sysrststat_Get	SYSRSTSTAT: System reset status register
SYSCON_systckcal	Register SYSTCKCAL: System tick counter calibration
SYSCON_systckcal_Get	SYSTCKCAL: System tick counter calibration
SYSCON_systckcal_Update	Updater for SYSTCKCAL register.
SYSCON_uartclkdiv	Register UARTCLKDIV: UART clock divder
SYSCON_uartclkdiv_Get	UARTCLKDIV: UART clock divder
SYSCON_uartclkdiv_Update	Updater for UARTCLKDIV register.
SYSCON_wdtclkdiv	Register WDTCLKDIV: WDT clock divider
SYSCON_wdtclkdiv_Get	WDTCLKDIV: WDT clock divider
SYSCON_wdtclkdiv_Update	Updater for WDTCLKDIV register.
SYSCON_wdtclksel	Register WDTCLKSEL: WDT clock source select
SYSCON_wdtclksel_Get	WDTCLKSEL: WDT clock source select
SYSCON_wdtclksel_Update	Updater for WDTCLKSEL register.
SYSCON_wdtclkuen	Register WDTCLKUEN: WDT clock source update enable
SYSCON_wdtclkuen_Get	WDTCLKUEN: WDT clock source update enable
SYSCON_wdtclkuen_Update	Updater for WDTCLKUEN register.
SYSCON_wdtoscctrl	Register WDTOSCCTRL: Watchdog oscillator control
SYSCON_wdtoscctrl_Get	WDTOSCCTRL: Watchdog oscillator control
SYSCON_wdtoscctrl_Update	Updater for WDTOSCCTRL register.
UART	Product name title=UM10398 Chapter title=LPC111x/LPC11Cxx UART Modification date=9/19/2011 Major revision=7 Minor revision=not available
UART_acr	Register ACR: Auto-baud Control Register. Contains controls for the auto-baud feature.
UART_acr_Get	ACR: Auto-baud Control Register. Contains controls for the auto-baud feature.
UART_acr_Update	Updater for ACR register.
UART_dll	Register DLL: Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)
UART_dll_Get	DLL: Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)
UART_dll_Update	Updater for DLL register.
UART_dlm	Register DLM: Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)
UART_dlm_Get	DLM: Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)
UART_dlm_Update	Updater for DLM register.
UART_fcr	Register FCR: FIFO Control Register. Controls UART FIFO usage and modes.
UART_fcr_Update	Updater for FCR register.
UART_fdr	Register FDR: Fractional Divider Register. Generates a clock input for the baud rate divider.
UART_fdr_Get	FDR: Fractional Divider Register. Generates a clock input for the baud rate divider.
UART_fdr_Update	Updater for FDR register.
UART_ier	Register IER: Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. (DLAB=0)
UART_ier_Get	IER: Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. (DLAB=0)
UART_ier_Update	Updater for IER register.
UART_iir	Register IIR: Interrupt ID Register. Identifies which interrupt(s) are pending.
UART_iir_Get	IIR: Interrupt ID Register. Identifies which interrupt(s) are pending.
UART_lcr	Register LCR: Line Control Register. Contains controls for frame formatting and break generation.
UART_lcr_Get	LCR: Line Control Register. Contains controls for frame formatting and break generation.
UART_lcr_Update	Updater for LCR register.
UART_lsr	Register LSR: Line Status Register. Contains flags for transmit and receive status, including line errors.
UART_lsr_Get	LSR: Line Status Register. Contains flags for transmit and receive status, including line errors.
UART_mcr	Register MCR: Modem control register
UART_mcr_Get	MCR: Modem control register
UART_mcr_Update	Updater for MCR register.
UART_msr	Register MSR: Modem status register
UART_msr_Get	MSR: Modem status register
UART_rbr	Register RBR: Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)
UART_rbr_Get	RBR: Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)
UART_rs485adrmatch	Register RS485ADRMATCH: RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
UART_rs485adrmatch_Get	RS485ADRMATCH: RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
UART_rs485adrmatch_Update	Updater for RS485ADRMATCH register.
UART_rs485ctrl	Register RS485CTRL: RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
UART_rs485ctrl_Get	RS485CTRL: RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
UART_rs485ctrl_Update	Updater for RS485CTRL register.
UART_rs485dly	Register RS485DLY: RS-485/EIA-485 direction control delay.
UART_rs485dly_Get	RS485DLY: RS-485/EIA-485 direction control delay.
UART_rs485dly_Update	Updater for RS485DLY register.
UART_scr	Register SCR: Scratch Pad Register. Eight-bit temporary storage for software.
UART_scr_Get	SCR: Scratch Pad Register. Eight-bit temporary storage for software.
UART_scr_Update	Updater for SCR register.
UART_ter	Register TER: Transmit Enable Register. Turns off UART transmitter for use with software flow control.
UART_ter_Get	TER: Transmit Enable Register. Turns off UART transmitter for use with software flow control.
UART_ter_Update	Updater for TER register.
UART_thr	Register THR: Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)
UART_thr_Update	Updater for THR register.
WWDT	Product name title=UM10398 Chapter title=LPC111x/LPC11Cxx Windowed WatchDog Timer (WDT) Modification date=9/19/2011 Major revision=6 Minor revision=not available
WWDT_wdfeed	Register WDFEED: Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.
WWDT_wdfeed_Update	Updater for WDFEED register.
WWDT_wdmod	Register WDMOD: Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.
WWDT_wdmod_Get	WDMOD: Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.
WWDT_wdmod_Update	Updater for WDMOD register.
WWDT_wdtc	Register WDTC: Watchdog timer constant register. This register determines the time-out value.
WWDT_wdtc_Get	WDTC: Watchdog timer constant register. This register determines the time-out value.
WWDT_wdtc_Update	Updater for WDTC register.
WWDT_wdtv	Register WDTV: Watchdog timer value register. This register reads out the current value of the Watchdog timer.
WWDT_wdtv_Get	WDTV: Watchdog timer value register. This register reads out the current value of the Watchdog timer.
WWDT_wdwarnint	Register WDWARNINT: Watchdog Warning Interrupt compare value.
WWDT_wdwarnint_Get	WDWARNINT: Watchdog Warning Interrupt compare value.
WWDT_wdwarnint_Update	Updater for WDWARNINT register.
WWDT_wdwindow	Register WDWINDOW: Watchdog Window compare value.
WWDT_wdwindow_Get	WDWINDOW: Watchdog Window compare value.
WWDT_wdwindow_Update	Updater for WDWINDOW register.

Enums

ADC_cr_burst
ADC_cr_clks
ADC_cr_edge
ADC_cr_start
CT16B0_ccr_cap0fe
CT16B0_ccr_cap0i
CT16B0_ccr_cap0re
CT16B0_ccr_cap1fe
CT16B0_ccr_cap1i
CT16B0_ccr_cap1re
CT16B0_ctcr_cis
CT16B0_ctcr_ctm
CT16B0_ctcr_selcc
CT16B0_emr_emc0
CT16B0_emr_emc1
CT16B0_emr_emc2
CT16B0_emr_emc3
CT16B0_mcr_mr0i
CT16B0_mcr_mr0r
CT16B0_mcr_mr0s
CT16B0_mcr_mr1i
CT16B0_mcr_mr1r
CT16B0_mcr_mr1s
CT16B0_mcr_mr2i
CT16B0_mcr_mr2r
CT16B0_mcr_mr2s
CT16B0_mcr_mr3i
CT16B0_mcr_mr3r
CT16B0_mcr_mr3s
CT16B0_pwmc_pwmen0
CT16B0_pwmc_pwmen1
CT16B0_pwmc_pwmen2
CT16B0_pwmc_pwmen3
CT32B0_ccr_cap0fe
CT32B0_ccr_cap0i
CT32B0_ccr_cap0re
CT32B0_ccr_cap1fe
CT32B0_ccr_cap1i
CT32B0_ccr_cap1re
CT32B0_ctcr_cis
CT32B0_ctcr_ctm
CT32B0_ctcr_selcc
CT32B0_emr_emc0
CT32B0_emr_emc1
CT32B0_emr_emc2
CT32B0_emr_emc3
CT32B0_mcr_mr0i
CT32B0_mcr_mr0r
CT32B0_mcr_mr0s
CT32B0_mcr_mr1i
CT32B0_mcr_mr1r
CT32B0_mcr_mr1s
CT32B0_mcr_mr2i
CT32B0_mcr_mr2r
CT32B0_mcr_mr2s
CT32B0_mcr_mr3i
CT32B0_mcr_mr3r
CT32B0_mcr_mr3s
CT32B0_pwmc_pwmen0
CT32B0_pwmc_pwmen1
CT32B0_pwmc_pwmen2
CT32B0_pwmc_pwmen3
C_CAN_cancntl_cce
C_CAN_cancntl_dar
C_CAN_cancntl_eie
C_CAN_cancntl_ie
C_CAN_cancntl_init
C_CAN_cancntl_sie
C_CAN_cancntl_test
C_CAN_canec_rp
C_CAN_canif1_arb2_dir
C_CAN_canif1_arb2_msgval
C_CAN_canif1_arb2_xtd
C_CAN_canif1_cmdmsk_r_arb
C_CAN_canif1_cmdmsk_r_clrintpnd
C_CAN_canif1_cmdmsk_r_ctrl
C_CAN_canif1_cmdmsk_r_data_a
C_CAN_canif1_cmdmsk_r_data_b
C_CAN_canif1_cmdmsk_r_mask
C_CAN_canif1_cmdmsk_r_newdat
C_CAN_canif1_cmdmsk_w_arb
C_CAN_canif1_cmdmsk_w_ctrl
C_CAN_canif1_cmdmsk_w_data_a
C_CAN_canif1_cmdmsk_w_data_b
C_CAN_canif1_cmdmsk_w_mask
C_CAN_canif1_cmdmsk_w_txrqst
C_CAN_canif1_cmdreq_busy
C_CAN_canif1_mctrl_eob
C_CAN_canif1_mctrl_intpnd
C_CAN_canif1_mctrl_msglst
C_CAN_canif1_mctrl_newdat
C_CAN_canif1_mctrl_rmten
C_CAN_canif1_mctrl_rxie
C_CAN_canif1_mctrl_txie
C_CAN_canif1_mctrl_txrqst
C_CAN_canif1_mctrl_umask
C_CAN_canif1_msk1_msk_15_0
C_CAN_canif1_msk2_mdir
C_CAN_canif1_msk2_msk_28_16
C_CAN_canif1_msk2_mxtd
C_CAN_canif2_arb2_dir
C_CAN_canif2_arb2_msgval
C_CAN_canif2_arb2_xtd
C_CAN_canif2_cmdmsk_r_arb
C_CAN_canif2_cmdmsk_r_clrintpnd
C_CAN_canif2_cmdmsk_r_ctrl
C_CAN_canif2_cmdmsk_r_data_a
C_CAN_canif2_cmdmsk_r_data_b
C_CAN_canif2_cmdmsk_r_mask
C_CAN_canif2_cmdmsk_r_newdat
C_CAN_canif2_cmdmsk_w_arb
C_CAN_canif2_cmdmsk_w_ctrl
C_CAN_canif2_cmdmsk_w_data_a
C_CAN_canif2_cmdmsk_w_data_b
C_CAN_canif2_cmdmsk_w_mask
C_CAN_canif2_cmdmsk_w_txrqst
C_CAN_canif2_cmdreq_busy
C_CAN_canif2_mctrl_eob
C_CAN_canif2_mctrl_intpnd
C_CAN_canif2_mctrl_msglst
C_CAN_canif2_mctrl_newdat
C_CAN_canif2_mctrl_rmten
C_CAN_canif2_mctrl_rxie
C_CAN_canif2_mctrl_txie
C_CAN_canif2_mctrl_txrqst
C_CAN_canif2_mctrl_umask
C_CAN_canif2_msk1_msk_15_0
C_CAN_canif2_msk2_mdir
C_CAN_canif2_msk2_msk_28_16
C_CAN_canif2_msk2_mxtd
C_CAN_canstat_boff
C_CAN_canstat_epass
C_CAN_canstat_ewarn
C_CAN_canstat_lec
C_CAN_canstat_rxok
C_CAN_canstat_txok
C_CAN_cantest_basic
C_CAN_cantest_lback
C_CAN_cantest_rx
C_CAN_cantest_silent
C_CAN_cantest_tx
FLASHCTRL_flashcfg_flashtim
FLASHCTRL_fmsstop_sig_start
I2C_mmctrl_ena_scl
I2C_mmctrl_match_all
I2C_mmctrl_mm_ena
IOCON_iocon_ct16b0_cap0_loc_ct16b0_cap0loc
IOCON_iocon_ct32b0_cap0_loc_ct32b0_cap0loc
IOCON_iocon_dcd_loc_dcdloc
IOCON_iocon_dsr_loc_dsrloc
IOCON_iocon_miso1_loc_miso1loc
IOCON_iocon_mosi1_loc_mosi1loc
IOCON_iocon_pio0_1_func
IOCON_iocon_pio0_1_hys
IOCON_iocon_pio0_1_mode
IOCON_iocon_pio0_1_od
IOCON_iocon_pio0_2_func
IOCON_iocon_pio0_2_hys
IOCON_iocon_pio0_2_mode
IOCON_iocon_pio0_2_od
IOCON_iocon_pio0_3_hys
IOCON_iocon_pio0_3_mode
IOCON_iocon_pio0_3_od
IOCON_iocon_pio0_4_func
IOCON_iocon_pio0_4_i2cmode
IOCON_iocon_pio0_5_func
IOCON_iocon_pio0_5_i2cmode
IOCON_iocon_pio0_6_func
IOCON_iocon_pio0_6_hys
IOCON_iocon_pio0_6_mode
IOCON_iocon_pio0_6_od
IOCON_iocon_pio0_7_func
IOCON_iocon_pio0_7_hys
IOCON_iocon_pio0_7_mode
IOCON_iocon_pio0_7_od
IOCON_iocon_pio0_8_func
IOCON_iocon_pio0_8_hys
IOCON_iocon_pio0_8_mode
IOCON_iocon_pio0_8_od
IOCON_iocon_pio0_9_func
IOCON_iocon_pio0_9_hys
IOCON_iocon_pio0_9_mode
IOCON_iocon_pio0_9_od
IOCON_iocon_pio1_10_admode
IOCON_iocon_pio1_10_func
IOCON_iocon_pio1_10_hys
IOCON_iocon_pio1_10_mode
IOCON_iocon_pio1_10_od
IOCON_iocon_pio1_11_admode
IOCON_iocon_pio1_11_func
IOCON_iocon_pio1_11_hys
IOCON_iocon_pio1_11_mode
IOCON_iocon_pio1_11_od
IOCON_iocon_pio1_4_admode
IOCON_iocon_pio1_4_func
IOCON_iocon_pio1_4_hys
IOCON_iocon_pio1_4_mode
IOCON_iocon_pio1_4_od
IOCON_iocon_pio1_5_func
IOCON_iocon_pio1_5_hys
IOCON_iocon_pio1_5_mode
IOCON_iocon_pio1_5_od
IOCON_iocon_pio1_6_func
IOCON_iocon_pio1_6_hys
IOCON_iocon_pio1_6_mode
IOCON_iocon_pio1_6_od
IOCON_iocon_pio1_7_func
IOCON_iocon_pio1_7_hys
IOCON_iocon_pio1_7_mode
IOCON_iocon_pio1_7_od
IOCON_iocon_pio1_8_func
IOCON_iocon_pio1_8_hys
IOCON_iocon_pio1_8_mode
IOCON_iocon_pio1_8_od
IOCON_iocon_pio1_9_func
IOCON_iocon_pio1_9_hys
IOCON_iocon_pio1_9_mode
IOCON_iocon_pio1_9_od
IOCON_iocon_pio2_0_func
IOCON_iocon_pio2_0_hys
IOCON_iocon_pio2_0_mode
IOCON_iocon_pio2_0_od
IOCON_iocon_pio2_10_hys
IOCON_iocon_pio2_10_mode
IOCON_iocon_pio2_10_od
IOCON_iocon_pio2_11_func
IOCON_iocon_pio2_11_hys
IOCON_iocon_pio2_11_mode
IOCON_iocon_pio2_11_od
IOCON_iocon_pio2_1_func
IOCON_iocon_pio2_1_hys
IOCON_iocon_pio2_1_mode
IOCON_iocon_pio2_1_od
IOCON_iocon_pio2_2_func
IOCON_iocon_pio2_2_hys
IOCON_iocon_pio2_2_mode
IOCON_iocon_pio2_2_od
IOCON_iocon_pio2_3_func
IOCON_iocon_pio2_3_hys
IOCON_iocon_pio2_3_mode
IOCON_iocon_pio2_3_od
IOCON_iocon_pio2_4_func
IOCON_iocon_pio2_4_hys
IOCON_iocon_pio2_4_mode
IOCON_iocon_pio2_4_od
IOCON_iocon_pio2_5_func
IOCON_iocon_pio2_5_hys
IOCON_iocon_pio2_5_mode
IOCON_iocon_pio2_5_od
IOCON_iocon_pio2_6_func
IOCON_iocon_pio2_6_hys
IOCON_iocon_pio2_6_mode
IOCON_iocon_pio2_6_od
IOCON_iocon_pio2_7_func
IOCON_iocon_pio2_7_hys
IOCON_iocon_pio2_7_mode
IOCON_iocon_pio2_7_od
IOCON_iocon_pio2_8_func
IOCON_iocon_pio2_8_hys
IOCON_iocon_pio2_8_mode
IOCON_iocon_pio2_8_od
IOCON_iocon_pio2_9_func
IOCON_iocon_pio2_9_hys
IOCON_iocon_pio2_9_mode
IOCON_iocon_pio2_9_od
IOCON_iocon_pio3_0_func
IOCON_iocon_pio3_0_hys
IOCON_iocon_pio3_0_mode
IOCON_iocon_pio3_0_od
IOCON_iocon_pio3_1_func
IOCON_iocon_pio3_1_hys
IOCON_iocon_pio3_1_mode
IOCON_iocon_pio3_1_od
IOCON_iocon_pio3_2_func
IOCON_iocon_pio3_2_hys
IOCON_iocon_pio3_2_mode
IOCON_iocon_pio3_2_od
IOCON_iocon_pio3_3_func
IOCON_iocon_pio3_3_hys
IOCON_iocon_pio3_3_mode
IOCON_iocon_pio3_3_od
IOCON_iocon_pio3_4_func
IOCON_iocon_pio3_4_hys
IOCON_iocon_pio3_4_mode
IOCON_iocon_pio3_4_od
IOCON_iocon_pio3_5_func
IOCON_iocon_pio3_5_hys
IOCON_iocon_pio3_5_mode
IOCON_iocon_pio3_5_od
IOCON_iocon_r_pio0_11_admode
IOCON_iocon_r_pio0_11_func
IOCON_iocon_r_pio0_11_hys
IOCON_iocon_r_pio0_11_mode
IOCON_iocon_r_pio0_11_od
IOCON_iocon_r_pio1_0_admode
IOCON_iocon_r_pio1_0_func
IOCON_iocon_r_pio1_0_hys
IOCON_iocon_r_pio1_0_mode
IOCON_iocon_r_pio1_0_od
IOCON_iocon_r_pio1_1_admode
IOCON_iocon_r_pio1_1_func
IOCON_iocon_r_pio1_1_hys
IOCON_iocon_r_pio1_1_mode
IOCON_iocon_r_pio1_1_od
IOCON_iocon_r_pio1_2_admode
IOCON_iocon_r_pio1_2_func
IOCON_iocon_r_pio1_2_hys
IOCON_iocon_r_pio1_2_mode
IOCON_iocon_r_pio1_2_od
IOCON_iocon_reset_pio0_0_func
IOCON_iocon_reset_pio0_0_hys
IOCON_iocon_reset_pio0_0_mode
IOCON_iocon_reset_pio0_0_od
IOCON_iocon_ri_loc_riloc
IOCON_iocon_rxd_loc_rxdloc
IOCON_iocon_sck0_loc_sckloc
IOCON_iocon_sck1_loc_sck1loc
IOCON_iocon_ssel1_loc_ssel1loc
IOCON_iocon_swclk_pio0_10_func
IOCON_iocon_swclk_pio0_10_hys
IOCON_iocon_swclk_pio0_10_mode
IOCON_iocon_swclk_pio0_10_od
IOCON_iocon_swdio_pio1_3_admode
IOCON_iocon_swdio_pio1_3_func
IOCON_iocon_swdio_pio1_3_hys
IOCON_iocon_swdio_pio1_3_mode
IOCON_iocon_swdio_pio1_3_od
PMU_gpreg4_wakeuphys
PMU_pcon_dpden
PMU_pcon_dpdflag
PMU_pcon_sleepflag
SPI0_cr0_cpha
SPI0_cr0_cpol
SPI0_cr0_dss
SPI0_cr0_frf
SPI0_cr1_lbm
SPI0_cr1_ms
SPI0_cr1_sse
SYSCON_bodctrl_bodintval
SYSCON_bodctrl_bodrstena
SYSCON_bodctrl_bodrstlev
SYSCON_clkoutclksel_sel
SYSCON_clkoutuen_ena
SYSCON_mainclksel_sel
SYSCON_mainclkuen_ena
SYSCON_pdawakecfg_adc_pd
SYSCON_pdawakecfg_bod_pd
SYSCON_pdawakecfg_flash_pd
SYSCON_pdawakecfg_irc_pd
SYSCON_pdawakecfg_ircout_pd
SYSCON_pdawakecfg_sysosc_pd
SYSCON_pdawakecfg_syspll_pd
SYSCON_pdawakecfg_wdtosc_pd
SYSCON_pdruncfg_adc_pd
SYSCON_pdruncfg_bod_pd
SYSCON_pdruncfg_flash_pd
SYSCON_pdruncfg_irc_pd
SYSCON_pdruncfg_ircout_pd
SYSCON_pdruncfg_sysosc_pd
SYSCON_pdruncfg_syspll_pd
SYSCON_pdruncfg_wdtosc_pd
SYSCON_pdsleepcfg_bod_pd
SYSCON_pdsleepcfg_wdtosc_pd
SYSCON_presetctrl_can_rst_n
SYSCON_presetctrl_i2c_rst_n
SYSCON_presetctrl_ssp0_rst_n
SYSCON_presetctrl_ssp1_rst_n
SYSCON_sysahbclkctrl_adc
SYSCON_sysahbclkctrl_can
SYSCON_sysahbclkctrl_ct16b0
SYSCON_sysahbclkctrl_ct16b1
SYSCON_sysahbclkctrl_ct32b0
SYSCON_sysahbclkctrl_ct32b1
SYSCON_sysahbclkctrl_flasharray
SYSCON_sysahbclkctrl_flashreg
SYSCON_sysahbclkctrl_gpio
SYSCON_sysahbclkctrl_i2c
SYSCON_sysahbclkctrl_iocon
SYSCON_sysahbclkctrl_ram
SYSCON_sysahbclkctrl_rom
SYSCON_sysahbclkctrl_ssp0
SYSCON_sysahbclkctrl_ssp1
SYSCON_sysahbclkctrl_uart
SYSCON_sysahbclkctrl_wdt
SYSCON_sysmemremap_map
SYSCON_sysoscctrl_bypass
SYSCON_sysoscctrl_freqrange
SYSCON_syspllclksel_sel
SYSCON_syspllclkuen_ena
SYSCON_syspllctrl_psel
SYSCON_syspllstat_lock
SYSCON_sysrststat_bod
SYSCON_sysrststat_extrst
SYSCON_sysrststat_por
SYSCON_sysrststat_sysrst
SYSCON_sysrststat_wdt
SYSCON_wdtclksel_sel
SYSCON_wdtclkuen_ena
SYSCON_wdtoscctrl_freqsel
UART_acr_abeointclr
UART_acr_abtointclr
UART_acr_autorestart
UART_acr_mode
UART_acr_start
UART_fcr_fifoen
UART_fcr_rxfifores
UART_fcr_rxtl
UART_fcr_txfifores
UART_ier_abeointen
UART_ier_abtointen
UART_ier_rbrie
UART_ier_rxlie
UART_ier_threie
UART_iir_intid
UART_iir_intstatus
UART_lcr_bc
UART_lcr_dlab
UART_lcr_pe
UART_lcr_ps
UART_lcr_sbs
UART_lcr_wls
UART_lsr_bi
UART_lsr_fe
UART_lsr_oe
UART_lsr_pe
UART_lsr_rdr
UART_lsr_rxfe
UART_lsr_temt
UART_lsr_thre
UART_mcr_ctsen
UART_mcr_rtsen
UART_msr_dcts
UART_msr_ddcd
UART_msr_ddsr
UART_msr_teri
UART_rs485ctrl_aaden
UART_rs485ctrl_dctrl
UART_rs485ctrl_nmmen
UART_rs485ctrl_oinv
UART_rs485ctrl_rxdis
UART_rs485ctrl_sel
WWDT_wdmod_wden
WWDT_wdmod_wdprotect
WWDT_wdmod_wdreset