Struct zinc_hal_lpc11xx::ioregs::SYSCON_ssp0clkdiv_Get

pub struct SYSCON_ssp0clkdiv_Get {
    // some fields omitted
}

SSP0CLKDIV: SPI0 clock divider

Methods

impl SYSCON_ssp0clkdiv_Get

fn new(reg: &SYSCON_ssp0clkdiv) -> SYSCON_ssp0clkdiv_Get

Create a getter reflecting the current value of the given register.

fn raw(&self) -> u32

Get the raw value of the register.

fn div(&self) -> u32

Get value of DIV field: SPI0_PCLK clock divider values 0: Disable SPI0_PCLK. 1: Divide by 1. to 255: Divide by 255.

Trait Implementations

impl Copy for SYSCON_ssp0clkdiv_Get

Derived Implementations

impl Clone for SYSCON_ssp0clkdiv_Get

fn clone(&self) -> SYSCON_ssp0clkdiv_Get

fn clone_from(&mut self, source: &Self)