Struct zinc_hal_lpc11xx::ioregs::CT16B0_ctcr_Get [] [src]

pub struct CT16B0_ctcr_Get {
    // some fields omitted
}

CTCR: Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.

Methods

impl CT16B0_ctcr_Get

fn new(reg: &CT16B0_ctcr) -> CT16B0_ctcr_Get

Create a getter reflecting the current value of the given register.

fn raw(&self) -> u32

Get the raw value of the register.

fn ctm(&self) -> CT16B0_ctcr_ctm

Get value of CTM field: Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC).

fn cis(&self) -> CT16B0_ctcr_cis

Get value of CIS field: Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.

fn encc(&self) -> bool

Get value of ENCC field: Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.

fn selcc(&self) -> CT16B0_ctcr_selcc

Get value of SELCC field: When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.

Trait Implementations

impl Copy for CT16B0_ctcr_Get

Derived Implementations

impl Clone for CT16B0_ctcr_Get

fn clone(&self) -> CT16B0_ctcr_Get

fn clone_from(&mut self, source: &Self)