Struct zinc_hal_lpc11xx::ioregs::CT16B0 [−] [src]

pub struct CT16B0;

Product name title=UM10398 Chapter title=LPC1100XL series: 16-bit counter/timer CT16B0/1 Modification date=2/22/2012 Major revision=8 Minor revision=not available

Methods

`impl CT16B0`

`fn ir() -> &'static mut CT16B0_ir`

Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.

`fn tcr() -> &'static mut CT16B0_tcr`

Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.

`fn tc() -> &'static mut CT16B0_tc`

Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.

`fn pr() -> &'static mut CT16B0_pr`

Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.

`fn pc() -> &'static mut CT16B0_pc`

Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.

`fn mcr() -> &'static mut CT16B0_mcr`

Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.

`fn mr0() -> &'static mut CT16B0_mr0`

Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.

`fn mr1() -> &'static mut CT16B0_mr1`

Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.

`fn mr2() -> &'static mut CT16B0_mr2`

Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.

`fn mr3() -> &'static mut CT16B0_mr3`

Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.

`fn ccr() -> &'static mut CT16B0_ccr`

Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

`fn cr0() -> &'static mut CT16B0_cr0`

Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.

`fn cr1() -> &'static mut CT16B0_cr1`

Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.

`fn emr() -> &'static mut CT16B0_emr`

External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT[2:0].

`fn ctcr() -> &'static mut CT16B0_ctcr`

Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.

`fn pwmc() -> &'static mut CT16B0_pwmc`

PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT[2:0].