Enum zinc_hal_lpc11xx::ioregs::I2C_mmctrl_ena_scl

pub enum I2C_mmctrl_ena_scl {
    High,
    Normal,
}

Variants

High	When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line.
Normal	When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]

Trait Implementations

Derived Implementations

impl PartialEq for I2C_mmctrl_ena_scl

fn eq(&self, __arg_0: &I2C_mmctrl_ena_scl) -> bool

fn ne(&self, __arg_0: &I2C_mmctrl_ena_scl) -> bool