Struct zinc_hal_lpc11xx::ioregs::SPI0_imsc_Get
[−]
[src]
pub struct SPI0_imsc_Get {
// some fields omitted
}IMSC: Interrupt Mask Set and Clear Register
Methods
impl SPI0_imsc_Get
fn new(reg: &SPI0_imsc) -> SPI0_imsc_Get
Create a getter reflecting the current value of the given register.
fn raw(&self) -> u32
Get the raw value of the register.
fn rorim(&self) -> bool
Get value of RORIM field: Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
fn rtim(&self) -> bool
Get value of RTIM field: Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]).
fn rxim(&self) -> bool
Get value of RXIM field: Software should set this bit to enable interrupt when the Rx FIFO is at least half full.
fn txim(&self) -> bool
Get value of TXIM field: Software should set this bit to enable interrupt when the Tx FIFO is at least half empty.