Struct zinc_hal_lpc11xx::ioregs::SPI0_cr0_Get
[−]
[src]
pub struct SPI0_cr0_Get {
// some fields omitted
}CR0: Control Register 0. Selects the serial clock rate, bus type, and data size.
Methods
impl SPI0_cr0_Get
fn new(reg: &SPI0_cr0) -> SPI0_cr0_Get
Create a getter reflecting the current value of the given register.
fn raw(&self) -> u32
Get the raw value of the register.
fn dss(&self) -> SPI0_cr0_dss
Get value of DSS field: Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.
fn frf(&self) -> SPI0_cr0_frf
Get value of FRF field: Frame Format.
fn cpol(&self) -> SPI0_cr0_cpol
Get value of CPOL field: Clock Out Polarity. This bit is only used in SPI mode.
fn cpha(&self) -> SPI0_cr0_cpha
Get value of CPHA field: Clock Out Phase. This bit is only used in SPI mode.
fn scr(&self) -> u32
Get value of SCR field: Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]).