Struct zinc_hal_lpc11xx::ioregs::ADC_cr_Get
[−]
[src]
pub struct ADC_cr_Get {
// some fields omitted
}CR: A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur.
Methods
impl ADC_cr_Get
fn new(reg: &ADC_cr) -> ADC_cr_Get
Create a getter reflecting the current value of the given register.
fn raw(&self) -> u32
Get the raw value of the register.
fn sel(&self) -> u32
Get value of SEL field: Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01).
fn clkdiv(&self) -> u32
Get value of CLKDIV field: The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.
fn burst(&self) -> ADC_cr_burst
Get value of BURST field: Burst mode
fn clks(&self) -> ADC_cr_clks
Get value of CLKS field: This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
fn start(&self) -> ADC_cr_start
Get value of START field: When the BURST bit is 0, these bits control whether and when an A/D conversion is started:
fn edge(&self) -> ADC_cr_edge
Get value of EDGE field: This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal.