Struct zinc_hal_lpc11xx::ioregs::CT32B0_ctcr_Get
[−]
[src]
pub struct CT32B0_ctcr_Get {
// some fields omitted
}CTCR: Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
Methods
impl CT32B0_ctcr_Get
fn new(reg: &CT32B0_ctcr) -> CT32B0_ctcr_Get
Create a getter reflecting the current value of the given register.
fn raw(&self) -> u32
Get the raw value of the register.
fn ctm(&self) -> CT32B0_ctcr_ctm
Get value of CTM field: Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge
fn cis(&self) -> CT32B0_ctcr_cis
Get value of CIS field: Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:
fn encc(&self) -> bool
Get value of ENCC field: Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.
fn selcc(&self) -> CT32B0_ctcr_selcc
Get value of SELCC field: When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.