Struct zinc_hal_lpc11xx::ioregs::SPI0_mis_Get
[−]
[src]
pub struct SPI0_mis_Get {
// some fields omitted
}MIS: Masked Interrupt Status Register
Methods
impl SPI0_mis_Get
fn new(reg: &SPI0_mis) -> SPI0_mis_Get
Create a getter reflecting the current value of the given register.
fn raw(&self) -> u32
Get the raw value of the register.
fn rormis(&self) -> bool
Get value of RORMIS field: This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.
fn rtmis(&self) -> bool
Get value of RTMIS field: This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]).
fn rxmis(&self) -> bool
Get value of RXMIS field: This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled.
fn txmis(&self) -> bool
Get value of TXMIS field: This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.