Struct zinc_hal_lpc11xx::ioregs::UART_lsr_Get
[−]
[src]
pub struct UART_lsr_Get {
// some fields omitted
}LSR: Line Status Register. Contains flags for transmit and receive status, including line errors.
Methods
impl UART_lsr_Get
fn new(reg: &UART_lsr) -> UART_lsr_Get
Create a getter reflecting the current value of the given register.
fn raw(&self) -> u32
Get the raw value of the register.
fn rdr(&self) -> UART_lsr_rdr
Get value of RDR field: Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART RBR FIFO is empty.
fn oe(&self) -> UART_lsr_oe
Get value of OE field: Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost.
fn pe(&self) -> UART_lsr_pe
Get value of PE field: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART RBR FIFO.
fn fe(&self) -> UART_lsr_fe
Get value of FE field: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO.
fn bi(&self) -> UART_lsr_bi
Get value of BI field: Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO.
fn thre(&self) -> UART_lsr_thre
Get value of THRE field: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART THR and is cleared on a THR write.
fn temt(&self) -> UART_lsr_temt
Get value of TEMT field: Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.
fn rxfe(&self) -> UART_lsr_rxfe
Get value of RXFE field: Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART FIFO.