Struct zinc_hal_lpc11xx::ioregs::SYSCON [−] [src]

pub struct SYSCON;

Product name title=UM10398 Chapter title=LPC111x/LPC11Cxx System configuration (SYSCON) Modification date=2/22/2012 Major revision=8 Minor revision=not available

Methods

`impl SYSCON`

`fn sysmemremap() -> &'static mut SYSCON_sysmemremap`

System memory remap

`fn presetctrl() -> &'static mut SYSCON_presetctrl`

Peripheral reset control

`fn syspllctrl() -> &'static mut SYSCON_syspllctrl`

System PLL control

`fn syspllstat() -> &'static mut SYSCON_syspllstat`

System PLL status

`fn sysoscctrl() -> &'static mut SYSCON_sysoscctrl`

System oscillator control

`fn wdtoscctrl() -> &'static mut SYSCON_wdtoscctrl`

Watchdog oscillator control

`fn ircctrl() -> &'static mut SYSCON_ircctrl`

IRC control

`fn sysrststat() -> &'static mut SYSCON_sysrststat`

System reset status register

`fn syspllclksel() -> &'static mut SYSCON_syspllclksel`

System PLL clock source select

`fn syspllclkuen() -> &'static mut SYSCON_syspllclkuen`

System PLL clock source update enable

`fn mainclksel() -> &'static mut SYSCON_mainclksel`

Main clock source select

`fn mainclkuen() -> &'static mut SYSCON_mainclkuen`

Main clock source update enable

`fn sysahbclkdiv() -> &'static mut SYSCON_sysahbclkdiv`

System AHB clock divider

`fn sysahbclkctrl() -> &'static mut SYSCON_sysahbclkctrl`

System AHB clock control

`fn ssp0clkdiv() -> &'static mut SYSCON_ssp0clkdiv`

SPI0 clock divider

`fn uartclkdiv() -> &'static mut SYSCON_uartclkdiv`

UART clock divder

`fn ssp1clkdiv() -> &'static mut SYSCON_ssp1clkdiv`

SPI1 clock divder

`fn wdtclksel() -> &'static mut SYSCON_wdtclksel`

WDT clock source select

`fn wdtclkuen() -> &'static mut SYSCON_wdtclkuen`

WDT clock source update enable

`fn wdtclkdiv() -> &'static mut SYSCON_wdtclkdiv`

WDT clock divider

`fn clkoutclksel() -> &'static mut SYSCON_clkoutclksel`

CLKOUT clock source select

`fn clkoutuen() -> &'static mut SYSCON_clkoutuen`

CLKOUT clock source update enable

`fn clkoutclkdiv() -> &'static mut SYSCON_clkoutclkdiv`

CLKOUT clock divider

`fn pioporcap0() -> &'static mut SYSCON_pioporcap0`

POR captured PIO status 0

`fn pioporcap1() -> &'static mut SYSCON_pioporcap1`

POR captured PIO status 1

`fn bodctrl() -> &'static mut SYSCON_bodctrl`

BOD control

`fn systckcal() -> &'static mut SYSCON_systckcal`

System tick counter calibration

`fn nmisrc() -> &'static mut SYSCON_nmisrc`

NMI source selection

`fn startaprp0() -> &'static mut SYSCON_startaprp0`

Start logic edge control register 0

`fn starterp0() -> &'static mut SYSCON_starterp0`

Start logic signal enable register 0

`fn startrsrp0clr() -> &'static mut SYSCON_startrsrp0clr`

Start logic reset register 0

`fn startsrp0() -> &'static mut SYSCON_startsrp0`

Start logic status register 0

`fn pdsleepcfg() -> &'static mut SYSCON_pdsleepcfg`

Power-down states in Deep-sleep mode

`fn pdawakecfg() -> &'static mut SYSCON_pdawakecfg`

Power-down states after wake-up from Deep-sleep mode

`fn pdruncfg() -> &'static mut SYSCON_pdruncfg`

Power-down configuration register

`fn device_id() -> &'static mut SYSCON_device_id`

Device ID register 0 for parts LPC1100, LPC1100C, LPC1100L.